1. Field of the Invention
The present invention relates to a semiconductor device having multilayer wiring, and more particularly to a method of forming interconnections between an upper wiring layer and a lower wiring layer.
2. Description of the Related Art
FIG. 14 shows a partial sectional view of a conventional semiconductor device having a lower conductive layer or wiring layer including a first conductive line or wire 61, an inter-layer dielectric film 62 with a through hole 63, and an upper conductive layer or wiring layer including a second conductive line or wire 64 that is connected to the lower-layer wire 61 by a metal plug filling the through hole 63. The through hole 63 has a depth d, radius r, and diameter 2r.
The multilayer wiring structure shown in FIG. 14 is fabricated as follows. First, a layer of metal is deposited on the entire surface of the device and patterned by photolithography and etching to form a lower-layer pattern of conductive lines 61. Next, the inter-layer dielectric film 62 is deposited on the entire surface and planarized by chemical-mechanical polishing (CMP). The inter-layer dielectric film 62 comprises a dielectric material such as silicate glass. The inter-layer dielectric film 62 is then etched to create through holes 63 at positions where the lower-layer conductive lines 61 will be connected to upper-layer conductive lines 64, and the through holes 62 are filled with metal. Another layer of metal is then deposited on the entire surface and patterned by photolithography and etching to create the upper-layer conductive lines 64.
As semiconductor device geometries have shrunk, so has the diameter (2r) of the through holes, and their aspect ratio (d/πr2) has increased. As a result, it has become difficult to assure the stable formation of a resist pattern for the small-diameter through holes in the photolithographic process, and to assure that the through holes will be etched to a constant depth during the etching process. The result is unreliable connections between the different wiring layers of a semiconductor device with multilayer wiring. The problem of the formation of a reliable connection structure for multilayer wiring has hindered progress toward devices with still smaller geometries.
A further problem is that if the depth d of the through holes is reduced as their diameter is reduced, the reduced spacing between wiring layers increases the parasitic capacitance of the wiring. The limiting dimensions for the stable formation of interconnections between different wiring layers in conventional semiconductor devices have been, for example, a through-hole diameter of one-fifth of a micrometer (2r=0.2 μm) and a through-hole depth of one-half of a micrometer (d=0.5 μm).